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| SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs Rev. 01 -- 9 February 2005 Product data sheet 1. General description The SC16C554B/554DB is a 4-channel Universal Asynchronous Receiver and Transmitter (QUART) used for serial data communications. Its principal function is to convert parallel data into serial data and vice versa. The UART can handle serial data rates up to 5 Mbit/s. It comes with an Intel(R) or Motorola(R) interface. The SC16C554B/554DB is pin compatible with the ST16C554 and TL16C554 and it will power-up to be functionally equivalent to the 16C454. Programming of control registers enables the added features of the SC16C554B/554DB. Some of these added features are the 16-byte receive and transmit FIFOs, four receive trigger levels. The SC16C554B/554DB also provides DMA mode data transfers through FIFO trigger levels and the TXRDY and RXRDY signals. On-board status registers provide the user with error indications, operational status, and modem interface control. System interrupts may be tailored to meet user requirements. An internal loop-back capability allows on-board diagnostics. The SC16C554B/554DB operates at 5 V, 3.3 V and 2.5 V, and the industrial temperature range, and is available in plastic PLCC68, LQFP64, and LQFP80 packages. 2. Features s s s s s s s s s s 4 channel UART 5 V, 3.3 V and 2.5 V operation Industrial temperature range (-40 C to +85 C) The SC16C554B is pin and software compatible with the industry-standard ST16C454/554, ST68C454/554, ST16C554, TL16C554 The SC16C554DB is pin and software compatible with ST16C554D, and software compatible with ST16C454/554, ST16C554, TL16C554 Up to 5 Mbit/s data rate at 5 V and 3.3 V, and 3 Mbit/s at 2.5 V 5 V tolerant inputs 16-byte transmit FIFO 16-byte receive FIFO with error flags Programmable auto-RTS and auto-CTS x In auto-CTS mode, CTS controls transmitter x In auto-RTS mode, RxFIFO contents and threshold control RTS Automatic hardware flow control (RTS/CTS) Software selectable Baud Rate Generator Four selectable Receive FIFO interrupt trigger levels Standard modem interface s s s s Philips Semiconductors SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs s Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun Break) s Transmit, Receive, Line Status, and Data Set interrupts independently controlled s Fully programmable character formatting: x 5, 6, 7, or 8-bit characters x Even, Odd, or No-Parity formats x 1, 112, or 2-stop bit x Baud generation (DC to 5 Mbit/s) s False start-bit detection s Complete status reporting capabilities s 3-state output TTL drive capabilities for bi-directional data bus and control bus s Line break generation and detection s Internal diagnostic capabilities: x Loop-back controls for communications link fault isolation s Prioritized interrupt system controls s Modem control functions (CTS, RTS, DSR, DTR, RI, CD). 3. Ordering information Table 1: Ordering information Package Name SC16C554DBIA68 SC16C554DBIB64 SC16C554BIB64 SC16C554BIB80 PLCC68 LQFP64 LQFP64 LQFP80 Description plastic leaded chip carrier; 68 leads plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm Version SOT188-2 SOT314-2 SOT314-2 SOT315-1 Type number 9397 750 13133 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 -- 9 February 2005 2 of 51 Philips Semiconductors SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 4. Block diagram SC16C554B/554DB TRANSMIT FIFO REGISTERS TRANSMIT SHIFT REGISTER TXA to TXD D0 to D7 IOR IOW RESET DATA BUS AND CONTROL LOGIC FLOW CONTROL LOGIC INTERCONNECT BUS LINES AND CONTROL SIGNALS RECEIVE FIFO REGISTERS RECEIVE SHIFT REGISTER RXA to RXD A0 to A2 CSA to CSD REGISTER SELECT LOGIC FLOW CONTROL LOGIC 16/68 DTRA to DTRD RTSA to RTSD INTA to INTD TXRDY RXRDY INTERRUPT CONTROL LOGIC CLOCK AND BAUD RATE GENERATOR MODEM CONTROL LOGIC CTSA to CTSD RIA to RID CDA to CDD DSRA to DSRD INTSEL 002aaa877 XTAL1 XTAL2 CLKSEL Fig 1. Block diagram of SC16C554B/554DB (16 mode) 9397 750 13133 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 -- 9 February 2005 3 of 51 Philips Semiconductors SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs SC16C554B/554DB TRANSMIT FIFO REGISTERS TRANSMIT SHIFT REGISTER TXA to TXD D0 to D7 R/W RESET DATA BUS AND CONTROL LOGIC FLOW CONTROL LOGIC INTERCONNECT BUS LINES AND CONTROL SIGNALS RECEIVE FIFO REGISTERS RECEIVE SHIFT REGISTER RXA to RXD A0 to A4 CS REGISTER SELECT LOGIC FLOW CONTROL LOGIC 16/68 DTRA to DTRD RTSA to RTSD IRQ TXRDY RXRDY INTERRUPT CONTROL LOGIC CLOCK AND BAUD RATE GENERATOR MODEM CONTROL LOGIC CTSA to CTSD RIA to RID CDA to CDD DSRA to DSRD 002aaa878 XTAL1 XTAL2 CLKSEL Fig 2. Block diagram of SC16C554B/554DB (68 mode) 9397 750 13133 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 -- 9 February 2005 4 of 51 Philips Semiconductors SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 5. Pinning information 5.1 Pinning 5.1.1 PLCC68 65 INTSEL GND DSRA 10 CTSA 11 DTRA 12 VCC 13 RTSA 14 INTA 15 CSA 16 TXA 17 IOW 18 TXB 19 CSB 20 INTB 21 RTSB 22 GND 23 DTRB 24 CTSB 25 DSRB 26 CDB 27 RIB 28 RXB 29 VCC 30 n.c. 31 A2 32 A1 33 A0 34 XTAL1 35 XTAL2 36 RESET 37 RXRDY 38 TXRDY 39 GND 40 RXC 41 RIC 42 CDC 43 61 CDD 60 DSRD 59 CTSD 58 DTRD 57 GND 56 RTSD 55 INTD 54 CSD 53 TXD 52 IOR 51 TXC 50 CSC 49 INTC 48 RTSC 47 VCC 46 DTRC 45 CTSC 44 DSRC 002aaa879 CDA 63 RXD RXA 64 VCC SC16C554DBIA68 16 mode Fig 3. Pin configuration for PLCC68 (16 mode) 9397 750 13133 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 -- 9 February 2005 62 RID RIA D7 D6 D5 D4 D3 68 D2 67 D1 66 D0 9 8 7 6 5 4 3 2 1 5 of 51 Philips Semiconductors SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs GND DSRA 10 CTSA 11 DTRA 12 VCC 13 RTSA 14 IRQ 15 CS 16 TXA 17 R/W 18 TXB 19 A3 20 n.c. 21 RTSB 22 GND 23 DTRB 24 CTSB 25 DSRB 26 CDB 27 RIB 28 RXB 29 VCC 30 16/68 31 A2 32 A1 33 A0 34 XTAL1 35 XTAL2 36 RESET 37 RXRDY 38 TXRDY 39 GND 40 RXC 41 RIC 42 CDC 43 61 CDD 60 DSRD 59 CTSD 58 DTRD 57 GND 56 RTSD 55 n.c. 54 n.c. 53 TXD 52 n.c. 51 TXC 50 A4 49 n.c. 48 RTSC 47 VCC 46 DTRC 45 CTSC 44 DSRC 002aaa880 CDA 63 RXD RXA 64 VCC SC16C554DBIA68 68 mode Fig 4. Pin configuration for PLCC68 (68 mode) 9397 750 13133 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 -- 9 February 2005 62 RID RIA 65 n.c. D7 D6 D5 D4 D3 68 D2 67 D1 66 D0 9 8 7 6 5 4 3 2 1 6 of 51 Philips Semiconductors SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 5.1.2 LQFP64 61 GND 49 CDD 64 CDA 51 RXD 62 RXA 52 VCC DSRA CTSA DTRA VCC RTSA INTA CSA TXA IOW 1 2 3 4 5 6 7 8 9 50 RID 63 RIA 60 D7 59 D6 58 D5 57 D4 56 D3 55 D2 54 D1 53 D0 48 DSRD 47 CTSD 46 DTRD 45 GND 44 RTSD 43 INTD 42 CSD 41 TXD 40 IOR 39 TXC 38 CSC 37 INTC 36 RTSC 35 VCC 34 DTRC 33 CTSC SC16C554BIB64 SC16C554DBIB64 TXB 10 CSB 11 INTB 12 RTSB 13 GND 14 DTRB 15 CTSB 16 DSRB 17 CDB 18 RIB 19 RXB 20 VCC 21 A2 22 A1 23 A0 24 XTAL1 25 XTAL2 26 RESET 27 GND 28 RXC 29 RIC 30 CDC 31 DSRC 32 002aaa881 Fig 5. Pin configuration for LQFP64 9397 750 13133 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 -- 9 February 2005 7 of 51 Philips Semiconductors SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 5.1.3 LQFP80 79 DSRD 62 DSRC 77 DTRD 64 DTRC 78 CTSD 75 RTSD 66 RTSC 63 CTSC 74 INTD 67 INTC 76 GND 73 CSD 68 CSC 72 TXD 69 TXC 65 VCC 70 IOR 80 n.c. 71 n.c. n.c. CDD RID RXD VCC INTSEL D0 D1 D2 1 2 3 4 5 6 7 8 9 61 n.c. 60 n.c. 59 CDC 58 RIC 57 RXC 56 GND 55 TXRDY 54 RXRDY 53 RESET 52 n.c. 51 XTAL2 50 XTAL1 49 n.c. 48 A0 47 A1 46 A2 45 VCC 44 RXB 43 RIB 42 CDB 41 n.c. n.c. 10 D3 11 D4 12 D5 13 D6 14 D7 15 GND 16 RXA 17 RIA 18 CDA 19 n.c. 20 SC16C554BIB80 n.c. 21 DSRA 22 CTSA 23 DTRA 24 VCC 25 RTSA 26 INTA 27 CSA 28 TXA 29 n.c. 30 TXA 31 IOW 32 TXB 33 CSB 34 INTB 35 RTSB 36 GND 37 DTRB 38 CTSB 39 n.c. 40 002aaa882 Fig 6. Pin configuration for LQFP80 9397 750 13133 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 -- 9 February 2005 8 of 51 Philips Semiconductors SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 5.2 Pin description Table 2: Symbol 16/68 Pin description Pin PLCC68 LQFP64 LQFP80 31 Type I Description 16/68 Interface type select (input with internal pull-up). This input provides the 16 (Intel) or 68 (Motorola) bus interface type select. The functions of IOR, IOW, INTA to INTD, and CSA to CSD are re-assigned with the logical state of this pin. When this pin is a logic 1, the 16 mode interface (16C554) is selected. When this pin is a logic 0, the 68 mode interface (68C554) is selected. When this pin is a logic 0, IOW is re-assigned to R/W, RESET is re-assigned to RESET, IOR is not used, and INTA to INTD are connected in a wire-OR configuration. The wire-OR outputs are connected internally to the open drain IRQ signal output. This pin is not available on 64-pin packages which operate in the 16 mode only. Address 0 select bit. Internal registers address selection in 16 and 68 modes. Address 1 select bit. Internal registers address selection in 16 and 68 modes. Address 2 select bit. Internal registers address selection in 16 and 68 modes. Address 3 to Address 4 select bits. When the 68 mode is selected, these pins are used to address or select individual UARTs (providing CS is a logic 0). In the 16 mode, these pins are re-assigned as chip selects, see CSB and CSC. Carrier Detect (active LOW). These inputs are associated with individual UART channels A through D. A logic 0 on this pin indicates that a carrier has been detected by the modem for that channel. Chip Select (active LOW). In the 68 mode, this pin functions as a multiple channel chip enable. In this case, all four UARTs (A to D) are enabled when the CS pin is a logic 0. An individual UART channel is selected by the data contents of address bits A3 to A4. when the 16 mode is selected (68-pin devices), this pin functions as CSA (see definition under CSA, CSB). Chip Select A, B, C, D (active LOW). This function is associated with the 16 mode only, and for individual channels `A' through `D'. When in 16 mode, these pins enable data transfers between the user CPU and the SC16C554B/554DB for the channel(s) addressed. Individual UART sections (A, B, C, D) are addressed by providing a logic 0 on the respective CSA to CSD pin. When the 68 mode is selected, the functions of these pins are re-assigned. 68 mode functions are described under their respective name/pin headings. Clear to Send (active LOW). These inputs are associated with individual UART channels A to D. A logic 0 on the CTS pin indicates the modem or data set is ready to accept transmit data from the SC16C554B/554DB. Status can be tested by reading MSR[4]. This pin only affects the transmit or receive operations when auto-CTS function is enabled via MCR[5] for hardware flow control operation. A0 A1 A2 A3, A4 34 33 32 20, 50 24 23 22 - 48 47 46 - I I I I CDA, CDB, CDC, CDD 9, 27, 43, 61 64, 18, 31, 49 19, 42, 59, 2 I CS 16 - - I CSA, CSB, CSC, CSD 16, 20, 50, 54 7, 11, 38, 42 28, 33, 68, 73 I CTSA, CTSB, 11, 25, CTSC, CTSD 45, 59 2, 16, 33, 47 23, 38, 63, 78 I 9397 750 13133 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 -- 9 February 2005 9 of 51 Philips Semiconductors SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs Table 2: Symbol D0 to D2, D3 to D7 Pin description ...continued Pin PLCC68 LQFP64 LQFP80 Type Description Data bus (bi-directional). These pins are the 8-bit, 3-state data bus for transferring information to or from the controlling CPU. D0 is the least significant bit and the first data bit in a transmit or receive serial data stream. Data Set Ready (active LOW). These inputs are associated with individual UART channels, A through D. A logic 0 on this pin indicates the modem or data set is powered-on and is ready for data exchange with the UART. This pin has no effect on the UART's transmit or receive operation. Data Terminal Ready (active LOW). These outputs are associated with individual UART channels, A through D. A logic 0 on this pin indicates that the SC16C554B/554DB is powered-on and ready. This pin can be controlled via the modem control register. Writing a logic 1 to MCR[0] will set the DTR output to logic 0, enabling the modem. This pin will be a logic 1 after writing a logic 0 to MCR[0], or after a reset. This pin has no effect on the UART's transmit or receive operation. Signal and power ground. Interrupt A, B, C, D (active HIGH). This function is associated with the 16 mode only. These pins provide individual channel interrupts INTA to INTD. INTA to INTD are enabled when MCR[3] is set to a logic 1, interrupts are enabled in the interrupt enable register (IER), and when an interrupt condition exists. Interrupt conditions include: receiver errors, available receiver buffer data, transmit buffer empty, or when a modem status flag is detected. When the 68 mode is selected, the functions of these pins are re-assigned. 68 mode functions are described under their respective name/pin headings. Interrupt Select (active HIGH, with internal pull-down). This function is associated with the 16 mode only. When the 16 mode is selected, this pin can be used in conjunction with MCR[3] to enable or disable the 3-state interrupts, INTA to INTD, or override MCR[3] and force continuous interrupts. Interrupt outputs are enabled continuously by making this pin a logic 1. Making this pin a logic 0 allows MCR[3] to control the 3-state interrupt output. In this mode, MCR[3] is set to a logic 1 to enable the 3-state outputs. This pin is disabled in the 68 mode. Due to pin limitations on the 64-pin packages, this pin is not available. To cover this limitation, the SC16C554DBIB64 version operates in the continuous interrupt enable mode by bonding this pin to VCC internally. The SC16C554BIB64 operates with MCR[3] control by bonding this pin to GND. Input/Output Read strobe (active LOW). This function is associated with the 16 mode only. A logic 0 transition on this pin will load the contents of an internal register defined by address bits A0 to A2 onto the SC16C554B/554DB data bus (D0 to D7) for access by external CPU. This pin is disabled in the 68 mode. 66 to 68, 53 to 55, 7 to 9, I/O 1 to 5 56 to 60 11 to 15 10, 26, DSRA, 44, 60 DSRB, DSRC, DSRD 1, 17, 32, 48 22, 39, 62, 79 I DTRA, 12, 24, DTRB, 46, 58 DTRC, DTRD 3, 15, 34, 46 24, 37, 64, 77 O GND INTA, INTB, INTC, INTD 6, 23, 40, 57 15, 21, 49, 55 14, 28, 45, 61 6, 12, 37, 43 16, 36, 56, 76 27, 34, 67, 74 I O INTSEL 65 - 6 I IOR 52 40 70 I 9397 750 13133 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 -- 9 February 2005 10 of 51 Philips Semiconductors SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs Table 2: Symbol IOW Pin description ...continued Pin PLCC68 LQFP64 LQFP80 18 9 31 Type I Description Input/Output Write strobe (active LOW). This function is associated with the 16 mode only. A logic 0 transition on this pin will transfer the contents of the data bus (D0 to D7) from the external CPU to an internal register that is defined by address bits A0 to A2. When the 68 mode is selected, this pin functions as R/W (see definition under R/W). Interrupt Request or Interrupt `A'. This function is associated with the 68 mode only. In the 68 mode, interrupts from UART channels A to D are wire-ORed internally to function as a single IRQ interrupt. This pin transitions to a logic 0 (if enabled by the interrupt enable register) whenever a UART channel(s) requires service. Individual channel interrupt status can be determined by addressing each channel through its associated internal register, using CS and A3 to A4. In the 68 mode, and external pull-up resistor must be connected between this pin and VCC. The function of this pin changes to INTA when operating in the 16 mode (see definition under INTA). not connected IRQ 15 - - O n.c. 21, 49, 52, 54, 55, 65 - 1, 10, 20, 21, 30, 40, 41, 49, 52, 60, 61, 71, 80 53 - RESET (RESET) 37 27 I Reset. In the 16 mode, a logic 1 on this pin will reset the internal registers and all the outputs. The UART transmitter output and the receiver input will be disabled during reset time. (See Section 7.10 "SC16C554B/554DB external reset conditions" for initialization details.) When 16/68 is a logic 0 (68 mode), this pin functions similarly, bus as an inverted reset interface signal, RESET. Ring Indicator (active LOW). These inputs are associated with individual UART channels, A to D. A logic 0 on this pin indicates the modem has received a ringing signal from the telephone line. A logic 1 transition on this input pin will generate an interrupt. Request to Send (active LOW). These outputs are associated with individual UART channels, A to D. A logic 0 on the RTS pin indicates the transmitter has data ready and waiting to send. Writing a logic 1 in the modem control register MCR[1] will set this pin to a logic 0, indicating data is available. After a reset this pin will be set to a logic 1. This pin only affects the transmit and receive operations when auto-RTS function is enabled via MCR[5] for hardware flow control operation. Read/Write strobe. This function is associated with the 68 mode only. This pin provides the combined functions for Read or Write strobes. Logic 1 = Read from UART register selected by CS and A0 to A4. Logic 0 = Write to UART register selected by CS and A0 to A4. RIA, RIB, RIC, RID 8, 28, 42, 62 63, 19, 30, 50 18, 43, 58, 3 I RTSA, RTSB, 14, 22, RTSC, RTSD 48, 56 5, 13, 36, 44 26, 35, 66, 75 O R/W 18 - - I 9397 750 13133 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 -- 9 February 2005 11 of 51 Philips Semiconductors SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs Table 2: Symbol RXA, RXB, RXC, RXD Pin description ...continued Pin PLCC68 LQFP64 LQFP80 7, 29, 41, 63 62, 20, 29, 51 17, 44, 57, 4 Type I Description Receive data input RXA to RXD. These inputs are associated with individual serial channel data to the SC16C554B/554DB. The RX signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. During the local loop-back mode, the RX input pin is disabled and TX data is connected to the UART RX input internally. Receive Ready (active LOW). RXRDY contains the wire-ORed status of all four receive channel FIFOs, RXRDYA to RXRDYD. A logic 0 indicates receive data ready status, that is, the RHR is full, or the FIFO has one or more RX characters available for unloading. This pin goes to a logic 1 when the FIFO/RHR is empty, or when there are no more characters available in either the FIFO or RHR. Individual channel RX status is read by examining individual internal registers via CS and A0 to A4 pin functions. Transmit data A, B, C, D. These outputs are associated with individual serial transmit channel data from the SC16C554B/554DB. The TX signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. During the local loop-back mode, the TX output pin is disabled and TX data is internally connected to the UART RX input. Transmit Ready (active LOW). TXRDY contains the wire-ORed status of all four transmit channel FIFOs, TXRDYA to TXRDYD. A logic 0 indicates a buffer ready status, that is, at least one location is empty and available in one of the TX channels (A to D). This pin goes to a logic 1 when all four channels have no more empty locations in the TX FIFO or THR. Individual channel TX status can be read by examining individual internal registers via CS and A0 to A4 pin functions. Power supply inputs. Crystal or external clock input. Functions as a crystal input or as an external clock input. A crystal can be connected between this pin and XTAL2 to form an internal oscillator circuit (see Figure 11). Alternatively, an external clock can be connected to this pin to provide custom data rates. (See Section 6.6 "Programmable baud rate generator".) Output of the crystal oscillator or buffered clock. (See also XTAL1.) Crystal oscillator output or buffered clock output. RXRDY 38 - 54 O TXA, TXB, TXC, TXD 17, 19, 51, 53 8, 10, 39, 41 29, 32, 69, 72 O TXRDY 39 - 55 O VCC XTAL1 13, 30, 47, 64 35 4, 21, 35, 52 25 5, 25, 45, 65 50 I I XTAL2 36 26 51 O 9397 750 13133 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 -- 9 February 2005 12 of 51 Philips Semiconductors SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 6. Functional description The SC16C554B/554DB provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-parallel data conversions for both the transmitter and receiver sections. These functions are necessary for converting the serial data stream into parallel data that is required with digital data systems. Synchronization for the serial data stream is accomplished by adding start and stop bits to the transmit data to form a data character. Data integrity is insured by attaching a parity bit to the data character. The parity bit is checked by the receiver for any transmission bit errors. The electronic circuitry to provide all these functions is fairly complex, especially when manufactured on a single integrated silicon chip. The SC16C554B/554DB represents such an integration with greatly enhanced features. The SC16C554B/554DB is fabricated with an advanced CMOS process to achieve low drain power and high speed requirements. The SC16C554B/554DB is an upward solution that provides 16 bytes of transmit and receive FIFO memory, instead of none in the 16C454. The SC16C554B/554DB is designed to work with high speed modems and shared network environments that require fast data processing time. Increased performance is realized in the SC16C554B/554DB by the larger transmit and receive FIFOs. This allows the external processor to handle more networking tasks within a given time. In addition, the four selectable levels of FIFO trigger interrupt is uniquely provided for maximum data throughput performance, especially when operating in a multi-channel environment. The combination of the above greatly reduces the bandwidth requirement of the external controlling CPU, increases performance, and reduces power consumption. The SC16C554B/554DBAI68 combines the package interface modes of the 16C454/554 and 68C454/554 series on a single integrated chip. The 16 mode interface is designed to operate with the Intel-type of microprocessor bus, while the 68 mode is intended to operate with Motorola and other popular microprocessors. Following a reset, the SC16C554B/554DBAI68 is downward compatible with the 16C454/554 or the 68C454/554, dependent on the state of the interface mode selection pin, 16/68. The SC16C554B/554DB is capable of operation to 1.5 Mbit/s with a 24 MHz crystal and up to 5 Mbit/s with an external clock input (at 3.3 V and 5 V; at 2.5 V the maximum speed is 3 Mbit/s). The rich feature set of the SC16C554B/554DB is available through internal registers. Selectable receive FIFO trigger levels, selectable TX and RX baud rates, and modem interface controls are all standard features. In the 16 mode, INTSEL and MCR[3] can be configured to provide a software controlled or continuous interrupt capability. Due to pin limitations of the 64-pin package, this feature is offered by two different LQFP64 packages. The SC16C554DB operates in the continuous interrupt enable mode by bonding INTSEL to VCC internally. The SC16C554B operates in conjunction with MCR[3] by bonding INTSEL to GND internally. 9397 750 13133 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 -- 9 February 2005 13 of 51 Philips Semiconductors SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 6.1 Interface options Two user interface modes are selectable for the PLCC68 package. These interface modes are designated as the `16 mode' and the `68 mode'. This nomenclature corresponds to the early 16C454/554 and 68C454/554 package interfaces respectively. 6.1.1 The 16 mode interface The 16 mode configures the package interface pins for connection as a standard 16 series (Intel) device and operates similar to the standard CPU interface available on the 16C454/554. In the 16 mode (pin 16/68 = logic 1), each UART is selected with individual chip select (CSx) pins, as shown in Table 3. Table 3: CSA 1 0 1 1 1 Serial port channel selection, 16 mode interface CSB 1 1 0 1 1 CSC 1 1 1 0 1 CSD 1 1 1 1 0 UART channel none A B C D 6.1.2 The 68 mode interface The 68 mode configures the package interface pins for connection with Motorola, and other popular microprocessor bus types. The interface operates similar to the 68C454/554. In this mode, the SC16C554B/554DB decodes two additional addresses, A3 to A4, to select one of the four UART ports. The A3 to A4 address decode function is used only when in the 68 mode (16/68 = logic 0), and is shown in Table 4. Table 4: CS 1 0 0 0 0 Serial port channel selection, 68 mode interface A4 n/a 0 0 1 1 A3 n/a 0 1 0 1 UART channel none A B C D 9397 750 13133 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 -- 9 February 2005 14 of 51 Philips Semiconductors SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 6.2 Internal registers The SC16C554B/554DB provides 12 internal registers for monitoring and control. These registers are shown in Table 5. These registers function as data holding registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control register (FCR), line status and control registers (LCR/LSR), modem status and control registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM), and a user accessible scratchpad register (SPR). Register functions are more fully described in the following paragraphs. Table 5: A2 0 0 0 0 1 1 1 1 0 0 [1] [2] Internal registers decoding A1 0 0 1 1 0 0 1 1 0 0 A0 0 1 0 1 0 1 0 1 0 1 Read mode Receive Holding Register Interrupt Enable Register Interrupt Status Register Line Control Register Modem Control Register Line Status Register Modem Status Register Scratchpad Register (DLL/DLM) [2] LSB of Divisor Latch MSB of Divisor Latch LSB of Divisor Latch MSB of Divisor Latch Write mode Transmit Holding Register Interrupt Enable Register FIFO Control Register Line Control Register Modem Control Register n/a n/a Scratchpad Register General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LSR, SPR) [1] Baud rate register set These registers are accessible only when LCR[7] is a logic 0. These registers are accessible only when LCR[7] is a logic 1. 6.3 FIFO operation The 16 byte transmit and receive data FIFOs are enabled by the FIFO Control Register (FCR) bit 0. With SC16C554B devices, the user can set the receive trigger level, but not the transmit trigger level. The receiver FIFO section includes a time-out function to ensure data is delivered to the external CPU. An interrupt is generated whenever the Receive Holding Register (RHR) has not been read following the loading of a character or the receive trigger level has not been reached. Table 6: Flow control mechanism INT pin activation 1 4 8 14 Negate RTS 4 8 12 14 Assert RTS 1 4 8 10 Selected trigger level (characters) 1 4 8 14 9397 750 13133 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 -- 9 February 2005 15 of 51 Philips Semiconductors SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 6.4 Autoflow control (see Figure 7) Autoflow control is comprised of auto-CTS and auto-RTS. With auto-CTS, the CTS input must be active before the transmitter FIFO can emit data. With auto-RTS, RTS becomes active when the receiver needs more data and notifies the sending serial device. When RTS is connected to CTS, data transmission does not occur unless the receiver FIFO has space for the data; thus, overrun errors are eliminated using UART 1 and UART 2 from a SC16C554B/554DB with the autoflow control enabled. If not, overrun errors occur when the transmit data rate exceeds the receiver FIFO read latency. ACE1 SERIAL TO PARALLEL RCV FIFO FLOW CONTROL D7 to D0 PARALLEL TO SERIAL XMT FIFO FLOW CONTROL CTS RTS TX RX RTS CTS ACE2 PARALLEL TO SERIAL XMT FIFO FLOW CONTROL D7 to D0 SERIAL TO PARALLEL RCV FIFO FLOW CONTROL 002aaa048 RX TX Fig 7. Autoflow control (auto-RTS and auto-CTS) example 6.4.1 Auto-RTS (see Figure 7) Auto-RTS data flow control originates in the receiver timing and control block (see block diagrams in Figure 1 and Figure 2) and is linked to the programmed receiver FIFO trigger level. When the receiver FIFO level reaches a trigger level of 1, 4, or 8 (see Figure 9), RTS is de-asserted. With trigger levels of 1, 4, and 8, the sending UART may send an additional byte after the trigger level is reached (assuming the sending UART has another byte to send) because it may not recognize the de-assertion of RTS until after it has begun sending the additional byte. RTS is automatically reasserted once the RX FIFO is emptied by reading the receiver buffer register. When the trigger level is 14 (see Figure 10), RTS is de-asserted after the first data bit of the 16th character is present on the RX line. RTS is reasserted when the RX FIFO has at least one available byte space. 6.4.2 Auto-CTS (see Figure 7) The transmitter circuitry checks CTS before sending the next data byte. When CTS is active, it sends the next byte. To stop the transmitter from sending the following byte, CTS must be released before the middle of the last stop bit that is currently being sent (see Figure 8). The auto-CTS function reduces interrupts to the host system. When flow control is enabled, CTS level changes do not trigger host interrupts because the device automatically controls its own transmitter. Without auto-CTS, the transmitter sends any data present in the transmit FIFO and a receiver overrun error may result. 9397 750 13133 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 -- 9 February 2005 16 of 51 Philips Semiconductors SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 6.4.3 Enabling autoflow control and auto-CTS Autoflow control is enabled by setting MCR[5] and MCR[1]. Table 7: MCR[5] 1 1 0 Enabling autoflow control and auto-CTS MCR[1] 1 0 X Selection auto RTS and CTS auto CTS disable 6.4.4 Auto-CTS and auto-RTS functional timing TX Start bits 0 to 7 Stop Start bits 0 to 7 Stop Start bits 0 to 7 Stop CTS 002aaa049 (1) When CTS is LOW, the transmitter keeps sending serial data out. (2) If CTS goes HIGH before the middle of the last stop bit of the current byte, the transmitter finishes sending the current byte, but is does not send the next byte. (3) When CTS goes from HIGH to LOW, the transmitter begins sending data again. Fig 8. CTS functional timing waveforms The receiver FIFO trigger level can be set to 1, 4, 8, or 14 bytes. These are described in Figure 9 and Figure 10. RX Start byte N Stop Start byte N + 1 Stop Start byte Stop RTS IOR (RD RBR) 1 2 N N+1 002aaa050 (1) N = RCV FIFO trigger level (1, 4, or 8 bytes). (2) The two blocks in dashed lines cover the case where an additional byte is sent as described in the preceding auto-RTS section. Fig 9. RTS functional timing waveforms, RCV FIFO trigger level = 1, 4, or 8 bytes 9397 750 13133 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 -- 9 February 2005 17 of 51 Philips Semiconductors SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs RX byte 14 byte 15 RTS released after the first data bit of byte 16 Start byte 16 Stop Start byte 18 Stop RTS IOR (RD RBR) 002aaa051 (1) RTS is de-asserted when the receiver receives the first data bit of the sixteenth byte. The receive FIFO is full after finishing the sixteenth byte. (2) RTS is asserted again when there is at least one byte of space available and no incoming byte is in processing, or there is more than one byte of space available. (3) When the receive FIFO is full, the first receive buffer register read re-asserts RTS. Fig 10. RTS functional timing waveforms, RCV FIFO trigger level = 14 bytes 6.5 Hardware/software and time-out interrupts Following a reset, if the transmitter interrupt is enabled, the SC16C554B/554DB will issue an interrupt to indicate that the Transmit Holding Register is empty. This interrupt must be serviced prior to continuing operations. The LSR register provides the current singular highest priority interrupt only. Only after servicing the higher pending interrupt will the lower priority interrupt(s) be reflected in the status register. Servicing the interrupt without investigating further interrupt conditions can result in data errors. When two interrupt conditions have the same priority, it is important to service these interrupts correctly. Receive Data Ready and Receive Time Out have the same interrupt priority (when enabled by IER[0]). The receiver issues an interrupt after the number of characters have reached the programmed trigger level. In this case, the SC16C554B/554DB FIFO may hold more characters than the programmed trigger level. Following the removal of a data byte, the user should re-check LSR[0] for additional characters. A Receive Time Out will not occur if the receive FIFO is empty. The time-out counter is reset at the center of each stop bit received or each time the receive holding register (RHR) is read. The actual time-out value is 4 character time. In the 16 mode for the PLCC68 package, the system/board designer can optionally provide software controlled 3-state interrupt operation. This is accomplished by INTSEL and MCR[3]. When INTSEL interface pin is left open or made a logic 0, MCR[3] controls the 3-state interrupt outputs, INTA to INTD. When INTSEL is a logic 1, MCR[3] has no effect on the INTA to INTD outputs, and the package operates with interrupt outputs enabled continuously. 6.6 Programmable baud rate generator The SC16C554B/554DB supports high speed modem technologies that have increased input data rates by employing data compression schemes. For example, a 33.6 kbit/s modem that employs data compression may require a 115.2 kbit/s input data rate. A 128.0 kbit/s ISDN modem that supports data compression may need an input data rate of 460.8 kbit/s. 9397 750 13133 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 -- 9 February 2005 18 of 51 Philips Semiconductors SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs A single baud rate generator is provided for the transmitter and receiver, allowing independent TX/RX channel control. The programmable Baud Rate Generator is capable of accepting an input clock up to 80 MHz (for 3.3 V and 5 V operation), as required for supporting a 5 Mbit/s data rate. The SC16C554B/554DB can be configured for internal or external clock operation. For internal clock oscillator operation, an industry standard microprocessor crystal (parallel resonant/22 pF to 33 pF load) is connected externally between the XTAL1 and XTAL2 pins (see Figure 11). Alternatively, an external clock can be connected to the XTAL1 pin to clock the internal baud rate generator for standard or custom rates (see Table 8). XTAL1 XTAL2 XTAL1 XTAL2 1.5 k X1 1.8432 MHz X1 1.8432 MHz C1 22 pF C2 33 pF C1 22 pF C2 47 pF 002aaa870 Fig 11. Crystal oscillator connection Programming the Baud Rate Generator registers DLM (MSB) and DLL (LSB) provides a user capability for selecting the desired final baud rate. Table 8: Baud rate generator programming table using a 7.3728 MHz clock User 16x clock divisor Decimal 200 1200 2400 4800 9600 19.2 k 38.4 k 76.8 k 153.6 k 230.4 k 460.8 k 2304 384 192 96 48 24 12 6 3 2 1 HEX 900 180 C0 60 30 18 0C 06 03 02 01 DLM program value (HEX) 09 01 00 00 00 00 00 00 00 00 00 DLL program value (HEX) 00 80 C0 60 30 18 0C 06 03 02 01 Output baud rate 9397 750 13133 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 -- 9 February 2005 19 of 51 Philips Semiconductors SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 6.7 DMA operation The SC16C554B/554DB FIFO trigger level provides additional flexibility to the user for block mode operation. LSR[5:6] provide an indication when the transmitter is empty or has an empty location(s). The user can optionally operate the transmit and receive FIFOs in the DMA mode (FCR[3]). When the transmit and receive FIFOs are enabled and the DMA mode is de-activated (DMA Mode 0), the SC16C554B/554DB activates the interrupt output pin for each data transmit or receive operation. When DMA mode is activated (DMA Mode 1), the user takes the advantage of block mode operation by loading or unloading the FIFO in a block sequence determined by the preset trigger level. In this mode, the SC16C554B/554DB sets the interrupt output pin when the characters in the receive FIFOs are above the receive trigger level. 6.8 Loop-back mode The internal loop-back capability allows on-board diagnostics. In the loop-back mode, the normal modem interface pins are disconnected and reconfigured for loop-back internally. MCR[0:3] register bits are used for controlling loop-back diagnostic testing. In the loop-back mode, OP1 and OP2 in the MCR register (bits 2:3) control the modem RI and CD inputs, respectively. MCR signals DTR and RTS (bits 0:1) are used to control the modem DSR and CTS inputs, respectively. The transmitter output (TX) and the receiver input (RX) are disconnected from their associated interface pins, and instead are connected together internally (see Figure 12). The CTS, DSR, CD, and RI are disconnected from their normal modem control input pins, and instead are connected internally to RTS, DTR, OP2 and OP1. Loop-back test data is entered into the transmit holding register via the user data bus interface, D0 to D7. The transmit UART serializes the data and passes the serial data to the receive UART via the internal loop-back connection. The receive UART converts the serial data back into parallel data that is then made available at the user data interface D0 to D7. The user optionally compares the received data to the initial transmitted data for verifying error-free operation of the UART TX/RX circuits. In this mode, the receiver and transmitter interrupts are fully operational. The Modem Control Interrupts are also operational. However, the interrupts can only be read using lower four bits of the Modem Status Register (MSR[0:3]) instead of the four Modem Status Register bits 4:7. The interrupts are still controlled by the IER. 9397 750 13133 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 -- 9 February 2005 20 of 51 Philips Semiconductors SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs SC16C554B/554DB TRANSMIT FIFO REGISTERS DATA BUS AND CONTROL LOGIC FLOW CONTROL LOGIC TRANSMIT SHIFT REGISTER TXA to TXD D0 to D7 IOR IOW RESET INTERCONNECT BUS LINES AND CONTROL SIGNALS RECEIVE FIFO REGISTERS RECEIVE SHIFT REGISTER MCR[4] = 1 RXA to RXD A0 to A2 CSA to CSD REGISTER SELECT LOGIC FLOW CONTROL LOGIC RTSA to RTSD CTSA to CTSD DTRA to DTRD MODEM CONTROL LOGIC INTA to INTD TXRDY RXRDY INTERRUPT CONTROL LOGIC CLOCK AND BAUD RATE GENERATOR DSRA to DSRD OP1A to OP1D RIA to RID OP2A to OP2D CDA to CDD 002aaa883 XTAL1 XTAL2 Fig 12. Internal loop-back mode diagram (16 mode) 9397 750 13133 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 -- 9 February 2005 21 of 51 Philips Semiconductors SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs SC16C554B/554DB TRANSMIT FIFO REGISTERS TRANSMIT SHIFT REGISTER TXA to TXD D0 to D7 R/W RESET FLOW CONTROL LOGIC INTERCONNECT BUS LINES AND CONTROL SIGNALS RECEIVE FIFO REGISTERS RECEIVE SHIFT REGISTER MCR[4] = 1 DATA BUS AND CONTROL LOGIC RXA to RXD A0 to A4 CS REGISTER SELECT LOGIC FLOW CONTROL LOGIC RTSA to RTSD CTSA to CTSD 16/68 DTRA to DTRD IRQ TXRDY RXRDY INTERRUPT CONTROL LOGIC CLOCK AND BAUD RATE GENERATOR MODEM CONTROL LOGIC DSRA to DSRD OP1A to OP1D RIA to RID OP2A to OP2D CDA to CDD 002aaa884 XTAL1 XTAL2 Fig 13. Internal loop-back mode diagram (68 mode) 9397 750 13133 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 -- 9 February 2005 22 of 51 Philips Semiconductors SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 7. Register descriptions Table 9 details the assigned bit functions for the SC16C554B/554DB internal registers. The assigned bit functions are more fully defined in Section 7.1 through Section 7.10. Table 9: SC16C554B/554DB internal registers Bit 6 bit 6 bit 6 0 Bit 5 bit 5 bit 5 0 Bit 4 bit 4 bit 4 0 Bit 3 bit 3 bit 3 modem status interrupt DMA mode select INT priority bit 2 parity enable Bit 2 bit 2 bit 2 Bit 1 bit 1 bit 1 Bit 0 bit 0 bit 0 receive holding register FIFO enable INT status word length bit 0 DTR set [2] XX XX 00 bit 7 bit 7 0 A2 A1 A0 Register Default [1] Bit 7 General Register 0 0 0 0 0 0 0 0 1 RHR THR IER receive transmit line status holding interrupt register XMIT RCVR FIFO reset FIFO reset INT priority bit 1 stop bits INT priority bit 0 word length bit 1 RTS 0 1 0 FCR 00 RCVR trigger (MSB) FIFOs enabled divisor latch enable 0 RCVR trigger (LSB) FIFOs enabled set break 0 reserved reserved 0 1 0 ISR 01 0 0 0 1 1 LCR 00 set parity even parity 1 0 0 MCR 00 autoflow loop back OP2, control INTx enable enable trans. holding empty DSR bit 5 bit 5 bit 13 break interrupt CTS bit 4 bit 4 bit 12 framing error CD bit 3 bit 3 bit 11 OP1 1 0 1 LSR 60 FIFO data error CD bit 7 bit 7 bit 15 trans. empty RI bit 6 bit 6 bit 14 parity error RI bit 2 bit 2 bit 10 overrun error DSR bit 1 bit 1 bit 9 receive data ready CTS bit 0 bit 0 bit 8 1 1 0 0 [1] [2] [3] 1 1 0 0 0 1 0 1 MSR SPR DLL DLM X0 FF XX XX Special Register set [3] The value shown represents the register's initialized HEX value; X = not applicable. These registers are accessible only when LCR[7] = 0. The Special Register set is accessible only when LCR[7] is set to a logic 1. 9397 750 13133 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 -- 9 February 2005 23 of 51 Philips Semiconductors SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 7.1 Transmit (THR) and Receive (RHR) Holding Registers The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and Transmit Shift Register (TSR). The status of the THR is provided in the Line Status Register (LSR). Writing to the THR transfers the contents of the data bus (D7 to D0) to the THR, providing that the THR or TSR is empty. The THR empty flag in the LSR register will be set to a logic 1 when the transmitter is empty or when data is transferred to the TSR. Note that a write operation can be performed when the THR empty flag is set (logic 0 = FIFO full; logic 1 = at least one FIFO location available). The serial receive section also contains an 8-bit Receive Holding Register (RHR). Receive data is removed from the SC16C554B/554DB and receive FIFO by reading the RHR register. The receive section provides a mechanism to prevent false starts. On the falling edge of a start or false start bit, an internal receiver counter starts counting clocks at the 16x clock rate. After 712 clocks, the start bit time should be shifted to the center of the start bit. At this time the start bit is sampled, and if it is still a logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver from assembling a false character. Receiver status codes will be posted in the LSR. 7.2 Interrupt Enable Register (IER) The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter empty, line status and modem status registers. These interrupts would normally be seen on the INTA to INTD output pins in the 16 mode, or on wire-OR IRQ output pin in the 68 mode. Table 10: Bit 7:4 3 Interrupt Enable Register bits description Description Reserved; set to `0'. Modem Status Interrupt. Logic 0 = Disable the modem status register interrupt (normal default condition). Logic 1 = Enable the modem status register interrupt. 2 IER[2] Receive Line Status interrupt. Logic 0 = Disable the receiver line status interrupt (normal default condition). Logic 1 = Enable the receiver line status interrupt. 1 IER[1] Transmit Holding Register interrupt. This interrupt will be issued whenever the THR is empty, and is associated with LSR[1]. Logic 0 = Disable the transmitter empty interrupt (normal default condition). Logic 1 = Enable the transmitter empty interrupt. 0 IER[0] Receive Holding Register interrupt. This interrupt will be issued when the FIFO has reached the programmed trigger level, or is cleared when the FIFO drops below the trigger level in the FIFO mode of operation. Logic 0 = Disable the receiver ready interrupt (normal default condition). Logic 1 = Enable the receiver ready interrupt. Symbol IER[7:4] IER[3] 9397 750 13133 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 -- 9 February 2005 24 of 51 Philips Semiconductors SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 7.2.1 IER versus Receive FIFO interrupt mode operation When the receive FIFO (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1) are enabled, the receive interrupts and register status will reflect the following: * The receive data available interrupts are issued to the external CPU when the FIFO has reached the programmed trigger level. It will be cleared when the FIFO drops below the programmed trigger level. * FIFO status will also be reflected in the user accessible ISR register when the FIFO trigger level is reached. Both the ISR register status bit and the interrupt will be cleared when the FIFO drops below the trigger level. * The data ready bit (LSR[0]) is set as soon as a character is transferred from the shift register to the receive FIFO. It is reset when the FIFO is empty. 7.2.2 IER versus Receive/Transmit FIFO polled mode operation When FCR[0] = logic 1, resetting IER[0:3] enables the SC16C554B/554DB in the FIFO polled mode of operation. Since the receiver and transmitter have separate bits in the LSR, either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). * * * * * LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO. LSR[1:4] will provide the type of errors encountered, if any. LSR[5] will indicate when the transmit FIFO is empty. LSR[6] will indicate when both the transmit FIFO and transmit shift register are empty. LSR[7] will indicate any FIFO data errors. 7.3 FIFO Control Register (FCR) This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger levels, and select the DMA mode. 7.3.1 DMA mode 7.3.1.1 Mode 0 (FCR bit 3 = 0) Set and enable the interrupt for each single transmit or receive operation, and is similar to the 16C454 mode. Transmit Ready (TXRDY) will go to a logic 0 whenever an empty transmit space is available in the Transmit Holding Register (THR). Receive Ready (RXRDY) will go to a logic 0 whenever the Receive Holding Register (RHR) is loaded with a character. 7.3.1.2 Mode 1 (FCR bit 3 = 1) Set and enable the interrupt in a block mode operation. The transmit interrupt is set when there are one or more FIFO locations empty. The receive interrupt is set when the receive FIFO fills to the programmed trigger level. However, the FIFO continues to fill regardless of the programmed level until the FIFO is full. RXRDY remains a logic 0 as long as the FIFO fill level is above the programmed trigger level. 9397 750 13133 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 -- 9 February 2005 25 of 51 Philips Semiconductors SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 7.3.2 FIFO mode Table 11: Bit 7:6 FIFO Control Register bits description Description RCVR trigger. These bits are used to set the trigger level for the receive FIFO interrupt. An interrupt is generated when the number of characters in the FIFO equals the programmed trigger level. However, the FIFO will continue to be loaded until it is full. Refer to Table 12. 5:4 3 FCR[5:4] FCR[3] Not used; initialized to logic 0. DMA mode select. Logic 0 = Set DMA mode `0' (normal default condition). Logic 1 = Set DMA mode `1' Transmit operation in mode `0': When the SC16C554B/554DB is in the 16C450 mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode (FIFOs enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there are no characters in the transmit FIFO or transmit holding register, the TXRDY pin will be a logic 0. Once active, the TXRDY pin will go to a logic 1 after the first character is loaded into the transmit holding register. Receive operation in mode `0': When the SC16C554B/554DB is in mode `0' (FCR[0] = logic 0), or in the FIFO mode (FCR[0] = logic 1; FCR[3] = logic 0) and there is at least one character in the receive FIFO, the RXRDY pin will be a logic 0. Once active, the RXRDY pin will go to a logic 1 when there are no more characters in the receiver. Transmit operation in mode `1': When the SC16C554B/554DB is in FIFO mode (FCR[0] = logic 1; FCR[3] = logic 1), the TXRDY pin will be a logic 1 when the transmit FIFO is completely full. It will be a logic 0 if one or more FIFO locations are empty. Receive operation in mode `1': When the SC16C554B/554DB is in FIFO mode (FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been reached, or a Receive Time-out has occurred, the RXRDY pin will go to a logic 0. Once activated, it will go to a logic 1 after there are no more characters in the FIFO. 2 FCR[2] XMIT FIFO reset. Logic 0 = No FIFO transmit reset (normal default condition). Logic 1 = Clears the contents of the transmit FIFO and resets the FIFO counter logic (the transmit shift register is not cleared or altered). This bit will return to a logic 0 after clearing the FIFO. 1 FCR[1] RCVR FIFO reset. Logic 0 = No FIFO receive reset (normal default condition). Logic 1 = Clears the contents of the receive FIFO and resets the FIFO counter logic (the receive shift register is not cleared or altered). This bit will return to a logic 0 after clearing the FIFO. 0 FCR[0] FIFO enable. Logic 0 = Disable the transmit and receive FIFO (normal default condition). Logic 1 = Enable the transmit and receive FIFO. This bit must be a `1' when other FCR bits are written to, or they will not be programmed. Symbol FCR[7:6] 9397 750 13133 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 -- 9 February 2005 26 of 51 Philips Semiconductors SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs RCVR trigger levels FCR[6] 0 1 0 1 RX FIFO trigger level 1 4 8 14 Table 12: FCR[7] 0 0 1 1 7.4 Interrupt Status Register (ISR) The SC16C554B/554DB provides four levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with four interrupt status bits. Performing a read cycle on the ISR will provide the user with the highest pending interrupt level to be serviced. No other interrupts are acknowledged until the pending interrupt is serviced. Whenever the interrupt status register is read, the interrupt status is cleared. However, it should be noted that only the current pending interrupt is cleared by the read. A lower level interrupt may be seen after re-reading the interrupt status bits. Table 13 "Interrupt source" shows the data values (bits 0 to 5) for the four prioritized interrupt levels and the interrupt sources associated with each of these interrupt levels. Table 13: Priority level 1 2 2 3 4 Interrupt source ISR[5] 0 0 0 0 0 ISR[4] 0 0 0 0 0 ISR[3] 0 0 1 0 0 ISR[2] 1 1 1 0 0 ISR[1] 1 0 0 1 0 ISR[0] 0 0 0 0 0 Source of the interrupt LSR (Receiver Line Status Register) RXRDY (Receive Data Ready) RXRDY (Receive Data time-out) TXRDY (Transmitter Holding Register Empty) MSR (Modem Status Register) Table 14: Bit 7:6 Interrupt Status Register bits description Symbol ISR[7:6] Description FIFOs enabled. These bits are set to a logic 0 when the FIFO is not being used. They are set to a logic 1 when the FIFOs are enabled. Logic 0 or cleared = default condition. Reserved; set to `0'. INT priority bits 2 to 0. These bits indicate the source for a pending interrupt at interrupt priority levels 1, 2, and 3 (see Table 13). Logic 0 or cleared = default condition. INT status. Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt service routine. Logic 1 = No interrupt pending (normal default condition). 5:4 3:1 ISR[5:4] ISR[3:1] 0 ISR[0] 9397 750 13133 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 -- 9 February 2005 27 of 51 Philips Semiconductors SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 7.5 Line Control Register (LCR) The Line Control Register is used to specify the asynchronous data communication format. The word length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. Table 15: Bit 7 Line Control Register bits description Symbol LCR[7] Description Divisor latch enable. The internal baud rate counter latch and Enhance Feature mode enable. Logic 0 = Divisor latch disabled (normal default condition). Logic 1 = Divisor latch enabled. 6 LCR[6] Set break. When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a logic 0 state). This condition exists until disabled by setting LCR[6] to a logic 0. Logic 0 = no TX break condition (normal default condition). Logic 1 = forces the transmitter output (TX) to a logic 0 for alerting the remote receiver to a line break condition. 5 LCR[5] Set parity. If the parity bit is enabled, LCR[5] selects the forced parity format. Programs the parity conditions (see Table 16). Logic 0 = parity is not forced (normal default condition). LCR[5] = logic 1 and LCR[4] = logic 0: parity bit is forced to a logical 1 for the transmit and receive data. LCR[5] = logic 1 and LCR[4] = logic 1: parity bit is forced to a logical 0 for the transmit and receive data. 4 LCR[4] Even parity. If the parity bit is enabled with LCR[3] set to a logic 1, LCR[4] selects the even or odd parity format. Logic 0 = Odd Parity is generated by forcing an odd number of logic 1s in the transmitted data. The receiver must be programmed to check the same format (normal default condition). Logic 1 = Even Parity is generated by forcing an even number of logic 1s in the transmitted data. The receiver must be programmed to check the same format. 3 LCR[3] Parity enable. Parity or no parity can be selected via this bit. Logic 0 = no parity (normal default condition). Logic 1 = a parity bit is generated during the transmission, receiver checks the data and parity for transmission errors. 2 LCR[2] Stop bits. The length of stop bit is specified by this bit in conjunction with the programmed word length (see Table 17). Logic 0 or cleared = default condition. 1:0 LCR[1:0] Word length bits 1, 0. These two bits specify the word length to be transmitted or received (see Table 18). Logic 0 or cleared = default condition. 9397 750 13133 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 -- 9 February 2005 28 of 51 Philips Semiconductors SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs LCR[5] parity selection LCR[4] X 0 1 0 1 LCR[3] 0 1 1 1 1 Parity selection no parity odd parity even parity forced parity `1' forced parity `0' Table 16: LCR[5] X 0 0 1 1 Table 17: LCR[2] 0 1 1 Table 18: LCR[1] 0 0 1 1 LCR[2] stop bit length Word length 5, 6, 7, 8 5 6, 7, 8 Stop bit length (bit times) 1 112 2 LCR[1:0] word length LCR[0] 0 1 0 1 Word length 5 6 7 8 9397 750 13133 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 -- 9 February 2005 29 of 51 Philips Semiconductors SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 7.6 Modem Control Register (MCR) This register controls the interface with the modem or a peripheral device. Table 19: Bit 7:6 5 4 Modem Control Register bits description Symbol MCR[7:6] MCR[5] MCR[4] Description Reserved; set to `0'. Autoflow control enable. Loop-back. Enable the local loop-back mode (diagnostics). In this mode the transmitter output (TX) and the receiver input (RX), CTS, DSR, CD, and RI are disconnected from the SC16C554B/554DB I/O pins. Internally the modem data and control pins are connected into a loop-back data configuration (see Figure 12). In this mode, the receiver and transmitter interrupts remain fully operational. The Modem Control Interrupts are also operational, but the interrupts' sources are switched to the lower four bits of the Modem Control. Interrupts continue to be controlled by the IER register. Logic 0 = Disable loop-back mode (normal default condition). Logic 1 = Enable local loop-back mode (diagnostics). 3 MCR[3] OP2, INTx enable. Used to control the modem CD signal in the loop-back mode. Logic 0 = Forces INTA to INTD outputs to the 3-state mode during the 16 mode (normal default condition). In the loop-back mode, sets OP2 (CD) internally to a logic 1. Logic 1 = Forces the INTA to INTD outputs to the active mode during the 16 mode. In the loop-back mode, sets OP2 (CD) internally to a logic 0. 2 MCR[2] OP1. This bit is used in the Loop-back mode only. In the loop-back mode, this bit is used to write the state of the modem RI interface signal via OP1. RTS Logic 0 = Force RTS output to a logic 1 (normal default condition). Logic 1 = Force RTS output to a logic 0. Automatic RTS may be used for hardware flow control by enabling MCR[5]. 0 MCR[0] DTR Logic 0 = Force DTR output to a logic 1 (normal default condition). Logic 1 = Force DTR output to a logic 0. 1 MCR[1] 9397 750 13133 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 -- 9 February 2005 30 of 51 Philips Semiconductors SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 7.7 Line Status Register (LSR) This register provides the status of data transfers between the SC16C554B/554DB and the CPU. Table 20: Bit 7 Line Status Register bits description Description FIFO data error. Logic 0 = No error (normal default condition). Logic 1 = At least one parity error, framing error or break indication is in the current FIFO data. This bit is cleared when LSR register is read. 6 LSR[6] THR and TSR empty. This bit is the Transmit Empty indicator. This bit is set to a logic 1 whenever the transmit holding register and the transmit shift register are both empty. It is reset to logic 0 whenever either the THR or TSR contains a data character. In the FIFO mode, this bit is set to `1' whenever the transmit FIFO and transmit shift register are both empty. THR empty. This bit is the Transmit Holding Register Empty indicator. This bit indicates that the UART is ready to accept a new character for transmission. In addition, this bit causes the UART to issue an interrupt to CPU when the THR interrupt enable is set. The THR bit is set to a logic 1 when a character is transferred from the transmit holding register into the transmitter shift register. The bit is reset to a logic 0 concurrently with the loading of the transmitter holding register by the CPU. In the FIFO mode, this bit is set when the transmit FIFO is empty; it is cleared when at least 1 byte is written to the transmit FIFO. Break interrupt. Logic 0 = No break condition (normal default condition). Logic 1 = The receiver received a break signal (RX was a logic 0 for one character frame time). In the FIFO mode, only one break character is loaded into the FIFO. 3 LSR[3] Framing error. Logic 0 = No framing error (normal default condition). Logic 1 = Framing error. The receive character did not have a valid stop bit(s). In the FIFO mode, this error is associated with the character at the top of the FIFO. 2 LSR[2] Parity error. Logic 0 = No parity error (normal default condition). Logic 1 = Parity error. The receive character does not have correct parity information and is suspect. In the FIFO mode, this error is associated with the character at the top of the FIFO. 1 LSR[1] Overrun error. Logic 0 = No overrun error (normal default condition). Logic 1 = Overrun error. A data overrun error occurred in the receive shift register. This happens when additional data arrives while the FIFO is full. In this case, the previous data in the shift register is overwritten. Note that under this condition, the data byte in the receive shift register is not transferred into the FIFO, therefore the data in the FIFO is not corrupted by the error. Symbol LSR[7] 5 LSR[5] 4 LSR[4] 9397 750 13133 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 -- 9 February 2005 31 of 51 Philips Semiconductors SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs Line Status Register bits description ...continued Description Receive data ready. Logic 0 = No data in receive holding register or FIFO (normal default condition). Logic 1 = Data has been received and is saved in the receive holding register or FIFO. Table 20: Bit 0 Symbol LSR[0] 7.8 Modem Status Register (MSR) This register provides the current state of the control interface signals from the modem, or other peripheral device to which the SC16C554B/554DB is connected. Four bits of this register are used to indicate the changed information. These bits are set to a logic 1 whenever a control input from the modem changes state. These bits are set to a logic 0 whenever the CPU reads this register. Table 21: Bit 7 Modem Status Register bits description Description CD (active HIGH, logical 1). Normally this bit is the complement of the CD input. In the loop-back mode this bit is equivalent to the OP2 bit in the MCR register. RI (active HIGH, logical 1). Normally this bit is the complement of the RI input. In the loop-back mode this bit is equivalent to the OP1 bit in the MCR register. DSR (active HIGH, logical 1). Normally this bit is the complement of the DSR input. In loop-back mode this bit is equivalent to the DTR bit in the MCR register. CTS (active HIGH, logical 1). CTS functions as hardware flow control signal input if it is enabled via MCR[5]. Flow control (when enabled) allows starting and stopping the transmissions based on the external modem CTS signal. A logic 1 at the CTS pin will stop SC16C554B/554DB transmissions as soon as current character has finished transmission. Normally MSR[4] is the complement of the CTS input. However, in the loop-back mode, this bit is equivalent to the RTS bit in the MCR register. CD [1] Symbol MSR[7] 6 MSR[6] 5 MSR[5] 4 MSR[4] 3 MSR[3] Logic 0 = No CD change (normal default condition). Logic 1 = The CD input to the SC16C554B/554DB has changed state since the last time it was read. A modem Status Interrupt will be generated. 2 MSR[2] RI [1] Logic 0 = No RI change (normal default condition). Logic 1 = The RI input to the SC16C554B/554DB has changed from a logic 0 to a logic 1. A modem Status Interrupt will be generated. 9397 750 13133 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 -- 9 February 2005 32 of 51 Philips Semiconductors SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs Modem Status Register bits description ...continued Description DSR [1] Table 21: Bit 1 Symbol MSR[1] Logic 0 = No DSR change (normal default condition). Logic 1 = The DSR input to the SC16C554B/554DB has changed state since the last time it was read. A modem Status Interrupt will be generated. 0 MSR[0] CTS [1] Logic 0 = No CTS change (normal default condition). Logic 1 = The CTS input to the SC16C554B/554DB has changed state since the last time it was read. A modem Status Interrupt will be generated. [1] Whenever any MSR[3:0] is set to logic 1, a Modem Status Interrupt will be generated. 7.9 Scratchpad Register (SPR) The SC16C554B/554DB provides a temporary data register to store 8 bits of user information. 7.10 SC16C554B/554DB external reset conditions Table 22: Register IER ISR LCR MCR LSR MSR FCR Table 23: Output TXA, TXB, TXC, TXD RTSA, RTSB, RTSC, RTSD DTRA, DTRB, DTRC, DTRD RXRDY TXRDY Reset state for registers Reset state IER[7:0] = 0 ISR[7:1] = 0; ISR[0] = 1 LCR[7:0] = 0 MCR[7:0] = 0 LSR[7] = 0; LSR[6:5] = 1; LSR[4:0] = 0 MSR[7:4] = input signals; MSR[3:0] = 0 FCR[7:0] = 0 Reset state for outputs Reset state HIGH HIGH HIGH HIGH LOW 9397 750 13133 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 -- 9 February 2005 33 of 51 Philips Semiconductors SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 8. Limiting values Table 24: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCC Vn Tamb Tstg Ptot(pack) Parameter supply voltage voltage at any pin ambient temperature storage temperature total power dissipation per package Conditions Min GND - 0.3 -40 -65 Max 7 VCC + 0.3 +85 +150 500 Unit V V C C mW 9397 750 13133 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 -- 9 February 2005 34 of 51 Philips Semiconductors SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 9. Static characteristics Table 25: Static characteristics Tamb = -40 C to +85 C; VCC = 2.5 V, 3.3 V or 5.0 V 10 %, unless otherwise specified. Symbol Parameter VIL(CK) VIH(CK) VIL VIH VOL LOW-level clock input voltage HIGH-level clock input voltage LOW-level input voltage (except XTAL1 clock) HIGH-level input voltage (except XTAL1 clock) LOW-level output voltage on all outputs [1] IOL = 5 mA (databus) IOL = 4 mA (other outputs) IOL = 2 mA (databus) IOL = 1.6 mA (other outputs) VOH HIGH-level output voltage IOH = -5 mA (databus) IOH = -1 mA (other outputs) IOH = -800 A (data bus) IOH = -400 A (other outputs) ILIL ICL ICC Ci Rpu(int) LOW-level input leakage current clock leakage supply current input capacitance internal pull-up resistance [2] f = 5 MHz Conditions Min -0.3 1.8 -0.3 1.6 1.85 1.85 500 2.5 V Typ Max Min +0.45 -0.3 VCC 2.4 3.3 V Typ Max +0.6 VCC +0.8 0.4 10 30 6 5 Min -0.5 3.0 -0.5 2.2 2.4 500 5.0 V Typ Max +0.6 VCC +0.8 0.4 10 30 6 5 V V V V V V V V V V V V A A mA pF k Unit +0.65 -0.3 0.4 0.4 10 30 4.5 5 2.0 2.0 500 [1] [2] Except XTAL2, VOL = 1 V typical. Refer to Table 2 "Pin description" on page 9 for a listing of pins having internal pull-up resistors. 9397 750 13133 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 -- 9 February 2005 35 of 51 Philips Semiconductors SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 10. Dynamic characteristics Table 26: Dynamic characteristics Tamb = -40 C to +85 C; VCC = 2.5 V, 3.3 V or 5.0 V 10 %, unless otherwise specified. Symbol Parameter t1w, t2w fXTAL t6s t6h t7d t7w t7h t9d t12d t12h t13d t13w t13h t15d t16s t16h t17d t18d t19d t20d t21d t22d t23d t24d t25d t26d t27d clock pulse duration oscillator/clock frequency address setup time address hold time IOR delay from chip select IOR strobe width chip select hold time from IOR read cycle delay delay from IOR to data data disable time IOW delay from chip select IOW strobe width chip select hold time from IOW write cycle delay data setup time data hold time delay from IOW to output 25 pF load delay to set interrupt from 25 pF load modem input delay to reset interrupt from IOR delay from stop to set interrupt delay from IOR to reset interrupt delay from start to set interrupt delay from IOW to transmit start delay from IOW to reset interrupt delay from stop to set RXRDY delay from IOR to reset RXRDY delay from IOW to set TXRDY 25 pF load 25 pF load 25 pF load 25 pF load 25 pF load 25 pF load [1] [2] Conditions Min 10 0 0 10 77 0 20 10 20 0 25 20 15 - 2.5 V Max 48 77 15 100 100 100 1 TRCLK [3] 3.3 V Min 6 0 0 10 26 0 20 10 20 0 25 20 5 Max 80 26 15 33 24 24 1 TRCLK [3] 5.0 V Min 6 0 0 10 23 0 20 10 15 0 20 15 5 Max 80 23 15 29 23 23 1 TRCLK [3] Unit ns MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 100 100 29 45 28 40 8 TRCLK 24 TRCLK 8 TRCLK 24 TRCLK 8 TRCLK 24 TRCLK ns [3] [3] [3] [3] [3] [3] - 100 1 TRCLK [3] - 45 1 TRCLK [3] - 40 1 TRCLK [3] ns ns ns ns 100 100 45 45 40 40 9397 750 13133 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 -- 9 February 2005 36 of 51 Philips Semiconductors SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs Table 26: Dynamic characteristics ...continued Tamb = -40 C to +85 C; VCC = 2.5 V, 3.3 V or 5.0 V 10 %, unless otherwise specified. Symbol Parameter t28d t30s t30w t30h t30d t31d t31h t32s t32h t32d t33s t33h tRESET N delay from start to reset TXRDY address setup time chip select strobe width address hold time read cycle delay delay from CS to data data disable time write strobe setup time write strobe hold time write cycle delay data setup time data hold time RESET pulse width baud rate divisor 25 pF load 25 pF load 25 pF load 25 pF load [1] Conditions Min 10 90 15 20 10 10 25 20 15 200 2.5 V Max 8 TRCLK [3] 3.3 V Min 10 26 15 20 10 10 25 15 5 40 Max 8 TRCLK [3] 5.0 V Min 10 23 15 20 10 10 20 15 5 40 Max 8 TRCLK [3] Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns 90 15 - 26 15 - 23 15 - 1 TRCLK 216 - 1 1 TRCLK 216 - 1 1 TRCLK 216 - 1 [3] TRCLK [3] [3] TRCLK [3] [3] TRCLK [3] [1] [2] [3] Applies to external clock, crystal oscillator max 24 MHz. Maximum frequency = ------RCLK is an internal signal derived from Divisor Latch LSB (DLL) and Divisor Latch MSB (DLM) divisor latches. 1 t 3w 10.1 Timing diagrams A0 to A4 t30s CS t32s t31h t30w t30h t30d R/W t31d D0 to D7 002aaa210 Fig 14. General read timing in 68 mode 9397 750 13133 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 -- 9 February 2005 37 of 51 Philips Semiconductors SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs A0 to A4 t30s t30w t30h CS t32s t32h t32d R/W t33s t33h D0 to D7 002aaa211 Fig 15. General write timing in 68 mode t6h valid address t6s t13h A0 to A2 CS t13d active t15d t13w active t16s t16h IOW D0 to D7 data 002aaa171 Fig 16. General write timing in 16 mode 9397 750 13133 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 -- 9 February 2005 38 of 51 Philips Semiconductors SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs t6h valid address t6s t7h A0 to A2 CS t7d active t9d t7w active t12d t12h IOR D0 to D7 data 002aaa172 Fig 17. General read timing in 16 mode IOW active t17d RTS DTR change of state change of state CD CTS DSR t18d change of state t18d change of state INT active t19d active active IOR active active t18d active RI change of state 002aaa352 Fig 18. Modem input/output timing 9397 750 13133 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 -- 9 February 2005 39 of 51 Philips Semiconductors SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs t2w EXTERNAL CLOCK t3w t1w 002aaa112 1 f XTAL = ------t 3w Fig 19. External clock timing start bit data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 D7 parity bit stop bit next data start bit RX 5 data bits 6 data bits 7 data bits INT t20d active t21d active IOR 16 baud rate clock 002aaa113 Fig 20. Receive timing 9397 750 13133 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 -- 9 February 2005 40 of 51 Philips Semiconductors SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs start bit data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 D7 parity bit stop bit next data start bit RX t25d RXRDY active data ready t26d IOR active 002aab063 Fig 21. Receive ready timing in non-FIFO mode start bit data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 D7 parity bit stop bit RX first byte that reaches the trigger level t25d RXRDY active data ready t26d IOR active 002aab064 Fig 22. Receive ready timing in FIFO mode 9397 750 13133 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 -- 9 February 2005 41 of 51 Philips Semiconductors SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs start bit data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 D7 parity bit stop bit next data start bit TX 5 data bits 6 data bits 7 data bits INT t22d t23d IOW active active transmitter ready t24d active 16 baud rate clock 002aaa116 Fig 23. Transmit timing start bit data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 D7 parity bit stop bit next data start bit TX IOW active t28d D0 to D7 byte #1 t27d TXRDY active transmitter ready 002aab062 transmitter not ready Fig 24. Transmit ready timing in non-FIFO mode 9397 750 13133 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 -- 9 February 2005 42 of 51 Philips Semiconductors SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs start bit data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 D7 parity bit stop bit TX 5 data bits 6 data bits 7 data bits IOW active t28d D0 to D7 byte #16 t27d TXRDY FIFO full 002aab061 Fig 25. Transmit ready timing in FIFO mode (DMA mode `1') 9397 750 13133 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 -- 9 February 2005 43 of 51 Philips Semiconductors SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 11. Package outline PLCC68: plastic leaded chip carrier; 68 leads SOT188-2 eD y 60 61 X 44 43 Z E A eE bp b1 wM 68 1 pin 1 index e E HE A A4 A1 (A 3) Lp detail X k 9 27 10 e D HD 26 ZD B vM A vMB 0 5 scale 10 mm DIMENSIONS (mm dimensions are derived from the original inch dimensions) A4 A1 UNIT A D(1) E(1) e A3 eD eE HD bp b1 max. min. mm inches 4.57 4.19 0.51 0.25 0.01 3.3 0.13 0.53 0.33 0.81 0.66 HE k Lp 1.44 1.02 v 0.18 w 0.18 y 0.1 ZD(1) ZE(1) max. max. 2.16 2.16 23.62 23.62 25.27 25.27 1.22 24.33 24.33 1.27 22.61 22.61 25.02 25.02 1.07 24.13 24.13 0.93 0.89 0.93 0.89 45 o 0.180 0.02 0.165 0.021 0.032 0.958 0.958 0.05 0.013 0.026 0.950 0.950 0.995 0.995 0.048 0.057 0.007 0.007 0.004 0.085 0.085 0.985 0.985 0.042 0.040 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT188-2 REFERENCES IEC 112E10 JEDEC MS-018 JEITA EDR-7319 EUROPEAN PROJECTION ISSUE DATE 99-12-27 01-11-14 Fig 26. PLCC68 package outline (SOT188-2) 9397 750 13133 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 -- 9 February 2005 44 of 51 Philips Semiconductors SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm SOT314-2 c y X A 48 49 33 32 ZE e E HE wM bp 64 1 pin 1 index 16 ZD bp D HD wM B vM B vM A 17 detail X L Lp A A2 A1 (A 3) e 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.20 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.18 0.12 D (1) 10.1 9.9 E (1) 10.1 9.9 e 0.5 HD HE L 1 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 1.45 1.05 1.45 1.05 7o o 0 12.15 12.15 11.85 11.85 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT314-2 REFERENCES IEC 136E10 JEDEC MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 00-01-19 03-02-25 Fig 27. LQFP64 package outline (SOT314-2) 9397 750 13133 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 -- 9 February 2005 45 of 51 Philips Semiconductors SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs LQFP80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm SOT315-1 c y X A 60 61 41 40 Z E e E HE wM bp pin 1 index 80 1 20 ZD bp D HD wM B vM B vM A 21 detail X Lp L A A2 A1 (A 3) e 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.16 0.04 A2 1.5 1.3 A3 0.25 bp 0.27 0.13 c 0.18 0.12 D (1) 12.1 11.9 E (1) 12.1 11.9 e 0.5 HD HE L 1 Lp 0.75 0.30 v 0.2 w 0.15 y 0.1 Z D (1) Z E (1) 1.45 1.05 1.45 1.05 7o o 0 14.15 14.15 13.85 13.85 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT315-1 REFERENCES IEC 136E15 JEDEC MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 00-01-19 03-02-25 Fig 28. LQFP80 package outline (SOT315-1) 9397 750 13133 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 -- 9 February 2005 46 of 51 Philips Semiconductors SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 12. Soldering 12.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 12.2 Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 C to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept: * below 225 C (SnPb process) or below 245 C (Pb-free process) - for all BGA, HTSSON..T and SSOP..T packages - for packages with a thickness 2.5 mm - for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages. * below 240 C (SnPb process) or below 260 C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times. 12.3 Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; 9397 750 13133 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 -- 9 February 2005 47 of 51 Philips Semiconductors SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 12.4 Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 C and 320 C. 12.5 Package related soldering information Table 27: Package [1] BGA, HTSSON..T [3], LBGA, LFBGA, SQFP, SSOP..T [3], TFBGA, VFBGA, XSON DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC [5], SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP CWQCCN..L [8], PMFP [9], WQCCN..L [8] [1] [2] Suitability of surface mount IC packages for wave and reflow soldering methods Soldering method Wave not suitable not suitable [4] Reflow [2] suitable suitable suitable not not recommended [5] [6] recommended [7] suitable suitable suitable not suitable not suitable For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. [3] 9397 750 13133 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 -- 9 February 2005 48 of 51 Philips Semiconductors SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs [4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. Hot bar soldering or manual soldering is suitable for PMFP packages. [5] [6] [7] [8] [9] 13. Abbreviations Table 28: Acronym CPU DMA FIFO ISDN QUART UART Abbreviations Description Central Processing Unit Direct Memory Access First In/First Out Integrated Service Digital Network 4-channel (Quad) Universal Asynchronous Receiver and Transmitter Universal Asynchronous Receiver and Transmitter 14. Revision history Table 29: Revision history Release date 20050209 Data sheet status Product data sheet Change notice Doc. number 9397 750 13133 Supersedes Document ID SC16C554B_554DB_1 9397 750 13133 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 -- 9 February 2005 49 of 51 Philips Semiconductors SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 15. Data sheet status Level I II Data sheet status [1] Objective data Preliminary data Product status [2] [3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). III Product data Production [1] [2] [3] Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 16. Definitions Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 18. Trademarks Intel -- is a registered trademark of Intel Corporation. Motorola -- is a registered trademark of Motorola, Inc. 17. Disclaimers Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors 19. Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com 9397 750 13133 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 -- 9 February 2005 50 of 51 Philips Semiconductors SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs 20. Contents 1 2 3 4 5 5.1 5.1.1 5.1.2 5.1.3 5.2 6 6.1 6.1.1 6.1.2 6.2 6.3 6.4 6.4.1 6.4.2 6.4.3 6.4.4 6.5 6.6 6.7 6.8 7 7.1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 PLCC68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 LQFP64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 LQFP80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 9 Functional description . . . . . . . . . . . . . . . . . . 13 Interface options . . . . . . . . . . . . . . . . . . . . . . . 14 The 16 mode interface . . . . . . . . . . . . . . . . . . 14 The 68 mode interface . . . . . . . . . . . . . . . . . . 14 Internal registers. . . . . . . . . . . . . . . . . . . . . . . 15 FIFO operation . . . . . . . . . . . . . . . . . . . . . . . . 15 Autoflow control (see Figure 7) . . . . . . . . . . . . 16 Auto-RTS (see Figure 7). . . . . . . . . . . . . . . . . 16 Auto-CTS (see Figure 7). . . . . . . . . . . . . . . . . 16 Enabling autoflow control and auto-CTS . . . . 17 Auto-CTS and auto-RTS functional timing . . . 17 Hardware/software and time-out interrupts. . . 18 Programmable baud rate generator . . . . . . . . 18 DMA operation . . . . . . . . . . . . . . . . . . . . . . . . 20 Loop-back mode . . . . . . . . . . . . . . . . . . . . . . . 20 Register descriptions . . . . . . . . . . . . . . . . . . . 23 Transmit (THR) and Receive (RHR) Holding Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.2 Interrupt Enable Register (IER) . . . . . . . . . . . 24 7.2.1 IER versus Receive FIFO interrupt mode operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.2.2 IER versus Receive/Transmit FIFO polled mode operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.3 FIFO Control Register (FCR) . . . . . . . . . . . . . 25 7.3.1 DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.3.1.1 Mode 0 (FCR bit 3 = 0) . . . . . . . . . . . . . . . . . . 25 7.3.1.2 Mode 1 (FCR bit 3 = 1) . . . . . . . . . . . . . . . . . . 25 7.3.2 FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.4 Interrupt Status Register (ISR) . . . . . . . . . . . . 27 7.5 Line Control Register (LCR) . . . . . . . . . . . . . . 28 7.6 Modem Control Register (MCR) . . . . . . . . . . . 30 7.7 Line Status Register (LSR) . . . . . . . . . . . . . . . 31 7.8 Modem Status Register (MSR). . . . . . . . . . . . 32 7.9 Scratchpad Register (SPR) . . . . . . . . . . . . . . 33 7.10 SC16C554B/554DB external reset conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8 9 10 10.1 11 12 12.1 12.2 12.3 12.4 12.5 13 14 15 16 17 18 19 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Static characteristics . . . . . . . . . . . . . . . . . . . Dynamic characteristics . . . . . . . . . . . . . . . . . Timing diagrams. . . . . . . . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . Manual soldering . . . . . . . . . . . . . . . . . . . . . . Package related soldering information . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Data sheet status. . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . 34 35 36 37 44 47 47 47 47 48 48 49 49 50 50 50 50 50 (c) Koninklijke Philips Electronics N.V. 2005 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 9 February 2005 Document number: 9397 750 13133 Published in The Netherlands |
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